A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel-load capability

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A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel-load capability. Draw a circuit for such a shift register. Write a Verilog code for the universal shift register with 4 bits using D flip-flops. Write a test bench to verify the functionality of it and show the timing diagram using the simulation in Vivado, Print out the Verilog code, test bench and the simulation results.

The Correct Answer and Explanation is :

A universal shift register is a versatile digital component capable of performing multiple operations, including shifting data left or right and parallel loading. It typically consists of multiple D flip-flops and multiplexers to control data flow based on mode selection inputs.

Verilog Code for 4-Bit Universal Shift Register:

module universal_shift_reg (
    input clk, rst_n,
    input [1:0] select, // Mode control: 00 = No change, 01 = Shift right, 10 = Shift left, 11 = Parallel load
    input [3:0] p_din,  // Parallel data input
    input s_left_din,   // Serial data input for left shift
    input s_right_din,  // Serial data input for right shift
    output reg [3:0] p_dout, // Parallel data output
    output s_left_dout, // Serial data output for left shift
    output s_right_dout // Serial data output for right shift
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            p_dout <= 4'b0000;
        else begin
            case (select)
                2'b01: p_dout <= {s_right_din, p_dout[3:1]}; // Shift right
                2'b10: p_dout <= {p_dout[2:0], s_left_din};  // Shift left
                2'b11: p_dout <= p_din; // Parallel load
                default: p_dout <= p_dout; // No change
            endcase
        end
    end

    assign s_left_dout = p_dout[0];
    assign s_right_dout = p_dout[3];
endmodule

Testbench for Simulation:

module tb_universal_shift_reg;
    reg clk, rst_n;
    reg [1:0] select;
    reg [3:0] p_din;
    reg s_left_din, s_right_din;
    wire [3:0] p_dout;
    wire s_left_dout, s_right_dout;

    universal_shift_reg uut (
        .clk(clk),
        .rst_n(rst_n),
        .select(select),
        .p_din(p_din),
        .s_left_din(s_left_din),
        .s_right_din(s_right_din),
        .p_dout(p_dout),
        .s_left_dout(s_left_dout),
        .s_right_dout(s_right_dout)
    );

    always #5 clk = ~clk;

    initial begin
        // Initialize signals
        clk = 0;
        rst_n = 0;
        select = 2'b00;
        p_din = 4'b1010;
        s_left_din = 1'b1;
        s_right_din = 1'b0;

        // Apply reset
        #10 rst_n = 1;

        // Test parallel load
        select = 2'b11; #10;
        select = 2'b00; #10;

        // Test shift right
        select = 2'b01; #10;
        select = 2'b00; #10;

        // Test shift left
        select = 2'b10; #10;
        select = 2'b00; #10;

        // Test no change
        select = 2'b00; #10;

        $finish;
    end
endmodule

Simulation and Timing Diagram:

To simulate the above Verilog code and generate a timing diagram in Vivado:

  1. Create a New Project:
  • Open Vivado and create a new project.
  • Add the universal_shift_reg and tb_universal_shift_reg files to the project.
  1. Compile the Design:
  • Run synthesis and implementation to compile the design.
  1. Run Simulation:
  • Launch the simulation tool within Vivado.
  • Set the testbench module (tb_universal_shift_reg) as the top module.
  • Run the simulation to observe the waveforms.
  1. View Timing Diagram:
  • In the simulation waveform viewer, observe the signals clk, rst_n, select, p_din, s_left_din, s_right_din, p_dout, s_left_dout, and s_right_dout.
  • Analyze the timing diagram to verify the functionality of the shift register in different modes.

Explanation:

The 4-bit universal shift register is designed to perform four operations based on the select input:

  • No Change (00): The register retains its current state.
  • Shift Right (01): The bits are shifted to the right, and the leftmost bit is replaced by s_right_din.
  • Shift Left (10): The bits are shifted to the left, and the rightmost bit is replaced by s_left_din.
  • Parallel Load (11): The register loads the 4-bit value from p_din.

The testbench initializes the inputs and applies various combinations of the select input to test each operation. The simulation results, viewed in Vivado’s waveform viewer, confirm that the shift register operates correctly in all modes.

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