Sketch pseudo-nMOS 3-input NAND and NOR gates. Label the transistor widths. What are the rising, falling, and average logical efforts of each gate?
The correct answer and explanation is :
The image above shows the schematic diagrams for the pseudo-nMOS 3-input NAND and NOR gates. In these circuits:
- Pseudo-nMOS 3-input NAND Gate: In this configuration, a single n-channel MOSFET is connected to the output and ground, while three p-channel MOSFETs are connected in parallel from the output to the positive voltage (VDD). The widths of the p-channel transistors are typically chosen to be larger than the n-channel transistor to balance the drive strengths. The gate output is low when all inputs are high, thus making the output high when any of the inputs are low (typical for a NAND gate).
- 3-input NOR Gate: This consists of three p-channel MOSFETs in series between VDD and the output, and three n-channel MOSFETs in parallel between the output and ground. This configuration produces a low output when any of the inputs are high and a high output when all inputs are low.
Logical Effort Calculations:
- Rising and Falling Effort:
- The rising and falling logical effort represents the ratio of the drive strength of the transistors in the gate to the drive strength of an inverter (which serves as a reference).
- Pseudo-nMOS 3-input NAND: The rising logical effort is higher due to the parallel p-channel transistors, while the falling effort is less than for the NOR gate since there is only one n-channel transistor to pull down the output.
- 3-input NOR: The rising effort is lower compared to the NAND gate, but the falling effort is higher due to the series connection of the p-channel transistors.
- Average Logical Effort:
- The average logical effort of each gate depends on both the rising and falling efforts, as well as the relative transistor widths used to balance the gate design. Typically, larger p-channel transistors would be used in the pseudo-nMOS design, leading to varying logical effort profiles.
The schematic image and further details can be analyzed to understand the relationship between the transistor widths, delays, and logical efforts of these gates.