Design a ripple-carry adder using NAND gates and inverters:
a) Draw a schematic for a full adder cell.
b) Size the transistors in a four-bit full adder using logical effort.
The correct answer and explanation is :
a) Schematic for a Full Adder Cell Using NAND Gates and Inverters
To design a full adder using NAND gates and inverters, we’ll need to construct the key logic functions for sum and carry outputs.
A full adder has three inputs: A, B, and Cin (carry-in), and two outputs: Sum and Carry-out (Cout).
- Sum (S): The sum is given by the following Boolean expression:
[
\text{Sum} = A \oplus B \oplus \text{Cin}
]
This XOR can be broken down using NAND gates and inverters. - Carry-out (Cout): The carry-out is given by:
[
\text{Cout} = (A \land B) \lor (B \land \text{Cin}) \lor (A \land \text{Cin})
]
This can be implemented using NAND gates.
Full Adder Using NAND Gates and Inverters
- First, use two NAND gates to compute the XOR of A and B.
- Then, use a third NAND gate to compute the XOR of the result of the previous XOR gate and Cin.
- The sum output is the final XOR result.
For the carry-out:
- Use three separate AND operations with NAND gates and inverters to compute the individual terms ( A \land B ), ( B \land \text{Cin} ), and ( A \land \text{Cin} ), and then OR them using NAND gates.
b) Sizing Transistors in a Four-Bit Full Adder Using Logical Effort
Logical Effort Approach:
The logical effort method involves sizing transistors based on the logical effort of gates to balance delay and ensure optimal performance. We can use the following steps to size the transistors:
- Logical Effort of a Gate: The logical effort of a gate measures how much effort the gate needs to drive its output relative to a simple inverter. A NAND gate with ( N ) inputs has a logical effort of ( N ). For instance, a 2-input NAND gate has a logical effort of 4.
- Sizing Transistors:
- The size of each transistor is determined by the logical effort of the gate it represents. The transistors should be sized such that the gate has a logical effort roughly equal to the optimal value for minimal delay.
- For CMOS, the transistor width is typically proportional to the gate’s logical effort. A wider transistor will have a lower resistance but will consume more area and power.
- Full Adder Sizing:
- In the case of a 4-bit full adder, we need to consider the delay of each of the gates involved in the sum and carry-out operations. Each bit of the adder will use the same logic as a single full adder.
- The total delay is given by the sum of the delays for each gate (i.e., XOR gates for the sum, AND and OR gates for the carry).
The ideal sizing follows the principle of minimum delay by balancing the logical effort across the different stages. Since XOR gates (which implement the sum) tend to have higher logical effort than NAND gates, they need larger transistor sizes for better performance. Similarly, the carry-out logic (which uses AND and OR operations) should be carefully sized to minimize delay.
In practice, we adjust the widths of the transistors in the full adder cells to minimize the overall delay and power consumption, aiming for a balanced gate sizing where the logical effort times the electrical effort (capacitance) is minimized for each stage in the adder.
Example Sizing:
For a 2-input NAND gate, the logical effort is 4, and for an inverter, it is 1. Transistor sizing is proportional to these values. For a 4-bit full adder, the carry logic will be slower due to multiple stages, so the carry gates need to be sized to drive higher capacitance effectively. This sizing will result in an optimized adder with minimal delay across all stages.