Assume a very simple microprocessor with 12 address lines with which we wish to implement only a quarter of the largest addressable memory using the same 512×8 memory chips. Physical memory must be placed on the upper half of the memory map.
a. What is the size of the memory implemented?
b. How many memory chips would be needed to implement this memory space?
c. How many lines would each chip require to address its internal memory cells?
d. How many lines would be required to select each chip?
e. Draw a simplified partial address decoding table listing all the memory chips as (MEM0, MEM1, MEM2…. etc.) and show the lines used for address decoding (chip selection) and those used to address internal memory cells. Fill the table appropriately with 1’s, 0’s, and X’s (don’t care).
The correct answer and explanation is :
Let’s break down the questions step by step, assuming that the largest addressable memory is determined by the 12 address lines of the microprocessor.
a. What is the size of the memory implemented?
The microprocessor has 12 address lines. The number of addressable locations is given by $2^{12} = 4096$ memory locations. The task is to implement a quarter of the largest addressable memory. This means the memory size to be implemented is:
$$
\frac{4096}{4} = 1024 \text{ memory locations}
$$
So, the size of the memory implemented is 1024 memory locations.
b. How many memory chips would be needed to implement this memory space?
Each memory chip has a configuration of 512×8. This means that each memory chip has 512 addressable locations, with each location storing 8 bits (1 byte).
To find how many memory chips are needed, divide the total number of memory locations (1024) by the number of locations per memory chip (512):
$$
\frac{1024}{512} = 2 \text{ chips}
$$
So, 2 memory chips are needed.
c. How many lines would each chip require to address its internal memory cells?
Each memory chip has 512 memory locations, and the number of address lines required to access 512 locations is given by:
$$
\log_2 512 = 9 \text{ address lines}
$$
So, each memory chip would require 9 address lines to access its internal memory cells.
d. How many lines would be required to select each chip?
Since the microprocessor has 12 address lines, and we’ve established that each chip requires 9 address lines for its internal memory, the remaining address lines (i.e., $12 – 9 = 3$) would be used to select which memory chip is being accessed. Thus, 3 address lines will be used for chip selection.
e. Draw a simplified partial address decoding table
The address decoding table helps us determine which chip is selected based on the address lines. As there are 2 chips (MEM0 and MEM1) and 3 address lines for chip selection, we need to decode these 3 lines to select the chips. The remaining 9 lines will be used to address internal memory cells for each chip.
Decoding Table:
| Address Bits (A11 A10 A9) | Chip Selected | Address Bits for Internal Memory (A8 A7 A6 A5 A4 A3 A2 A1 A0) |
|---|---|---|
| 000 | MEM0 | XXXXXX XXXXXX (A8 A7 A6 A5 A4 A3 A2 A1 A0) |
| 001 | MEM1 | XXXXXX XXXXXX (A8 A7 A6 A5 A4 A3 A2 A1 A0) |
| 010 | X | XXXXXX XXXXXX |
| 011 | X | XXXXXX XXXXXX |
| 100 | X | XXXXXX XXXXXX |
| 101 | X | XXXXXX XXXXXX |
| 110 | X | XXXXXX XXXXXX |
| 111 | X | XXXXXX XXXXXX |
Explanation:
- A11, A10, and A9 are used to select between different memory chips. They control which memory chip (MEM0 or MEM1) is selected.
- When A11, A10, and A9 are 000, MEM0 is selected.
- When A11, A10, and A9 are 001, MEM1 is selected.
- For all other combinations of A11, A10, and A9, no chip is selected.
- A8 to A0 are used to address the internal memory locations within each chip. The values of A8 to A0 will remain unchanged when selecting the chip; they will determine which of the 512 memory locations (in the range 0 to 511) within the selected chip is being accessed.
Summary:
- Memory size: 1024 memory locations.
- Memory chips: 2 chips are needed.
- Chip address lines: 9 address lines per chip.
- Chip selection lines: 3 address lines to select between chips.
- Address decoding table: A partial address decoding table is provided, showing how 3 bits select the chips, while the remaining bits address memory cells within each chip.
This design ensures that the memory is placed in the upper half of the addressable range, and the correct chips are selected based on the address provided by the microprocessor.