Using 64 × 8 ROM chips with an enable input, construct a 512 × 8 ROM with eight chips and a decoder.
The Correct Answer And Explanation is:
To construct a 512 × 8 ROM using 64 × 8 ROM chips (with an enable input), you will need:
- Eight 64 × 8 ROM chips
- A 3-to-8 line decoder
Correct Answer:
Use the 3 most significant address bits (A6, A5, A4) to drive a 3-to-8 decoder, which enables one of the eight ROM chips. Each ROM chip handles 64 addresses (2⁶), using the 6 least significant address bits (A3 to A0) as input. Connect the outputs of all ROM chips together in a wired-OR or tri-state configuration, depending on the chip type.
Detailed Explanation (300+ words):
A 64 × 8 ROM chip means it can store 64 words, each 8 bits wide. Since $64 = 2^6$, the ROM requires 6 address lines (A0 to A5). To build a 512 × 8 ROM, we need a total of 512 memory locations (i.e., $512 = 2^9$), each also 8 bits wide.
Thus, our goal is to create a ROM with:
- 9 address lines (A0 to A8)
- 512 memory locations
- 8 data bits per location
Since each chip stores 64 locations, and we need 512, we divide:
$$
\frac{512}{64} = 8 \text{ chips needed}
$$
To manage these 8 chips, we must select one chip at a time based on the address being accessed. This is where the decoder comes in.
Decoder Integration
We use the 3 most significant bits (A8, A7, A6) of the 9-bit address to drive a 3-to-8 decoder. Each output line of the decoder connects to the Enable (EN) input of a single ROM chip. The decoder activates only one output line at a time, based on the 3-bit input, enabling the corresponding ROM chip.
Address Lines to ROM Chips
- A5 to A0 go to the address inputs of all eight ROM chips (since they all share these lines).
- Only the ROM chip selected by the decoder (via its enable input) will be active and place data on the data bus.
- Outputs from all chips are connected in parallel, with only the selected chip allowed to drive the data bus (via tri-state outputs or output enable logic).
This method ensures the ROM behaves as a single 512 × 8 memory.