Memory Address Map and Direct Mapping
A computer employs RAM chips of 256 x 8 and ROM chips of 512 x 8. The computer system requires a total memory capacity of 2048 x 8 (2k), divided as follows:
1k bytes of RAM
1k bytes of ROM
Tasks:
Memory Address Map:
Create a memory address map showing the allocation of RAM and ROM within the 2k memory space.
Hexadecimal Address Range:
Specify the address range in hexadecimal format for both RAM and ROM.
Hit Ratio Explanation:
Define and calculate the hit ratio in the context of memory systems.
Direct Mapping Method:
Explain the concept of direct mapping with a suitable diagram.
Part 2: Virtual Memory and Paging
Virtual Memory Concept:
Explain the concept of virtual memory, including its advantages and mechanisms.
Paging Mechanism:
Discuss paging in detail, focusing on how it enables efficient memory management in modern systems.
Additional Task:
Given the page reference string:
7, 3, 1, 1, 5, 6, 3, 3, 3, 4, 6
Determine:
How many page faults occur using a specified page replacement algorithm (e.g., FIFO, LRU).
The Correct Answer and Explanation is:
Sure! Here’s a comprehensive answer (including all tasks and the 1000-word explanation) divided into Part 1: Memory Address Map and Direct Mapping and Part 2: Virtual Memory and Paging, concluding with page fault analysis.
Part 1: Memory Address Map and Direct Mapping
Memory Chips Configuration
- RAM chip size: 256 × 8 bits = 256 bytes
- ROM chip size: 512 × 8 bits = 512 bytes
- Required RAM: 1 KB = 1024 bytes → Needs 4 RAM chips (1024 / 256 = 4)
- Required ROM: 1 KB = 1024 bytes → Needs 2 ROM chips (1024 / 512 = 2)
Memory Address Map (2K Memory Space)
Total memory: 2048 × 8 = 2 KB = 0x000 to 0x7FF
We divide this memory into two equal parts:
- RAM: Lower half → 0x000 to 0x3FF
- ROM: Upper half → 0x400 to 0x7FF
Each block will be allocated sequentially to the number of required chips.
Memory Address Map Table
| Address Range (Hex) | Size | Memory Type | Chip Count | Chip Size |
|---|---|---|---|---|
| 0x000 to 0x0FF | 256 B | RAM | RAM Chip 1 | 256 × 8 |
| 0x100 to 0x1FF | 256 B | RAM | RAM Chip 2 | 256 × 8 |
| 0x200 to 0x2FF | 256 B | RAM | RAM Chip 3 | 256 × 8 |
| 0x300 to 0x3FF | 256 B | RAM | RAM Chip 4 | 256 × 8 |
| 0x400 to 0x5FF | 512 B | ROM | ROM Chip 1 | 512 × 8 |
| 0x600 to 0x7FF | 512 B | ROM | ROM Chip 2 | 512 × 8 |
Hexadecimal Address Ranges
- RAM: 0x000 to 0x3FF (1024 bytes or 1 KB)
- ROM: 0x400 to 0x7FF (1024 bytes or 1 KB)
Hit Ratio Explanation
Definition:
The hit ratio is the percentage of memory accesses that are found in the cache memory.
Formula:
Hit Ratio=Number of Cache HitsTotal Memory Accesses=1−Miss Ratio\text{Hit Ratio} = \frac{\text{Number of Cache Hits}}{\text{Total Memory Accesses}} = 1 – \text{Miss Ratio}
Example:
If 1000 memory accesses occur and 850 are found in the cache: Hit Ratio=8501000=0.85=85%\text{Hit Ratio} = \frac{850}{1000} = 0.85 = 85\%
A higher hit ratio indicates better cache performance and faster system operation.
Direct Mapping Method
Direct mapping is a technique for placing main memory blocks into cache blocks.
How it works:
- Each main memory block maps to exactly one cache line.
- If two blocks map to the same cache line, the new one overwrites the old.
Formula:
Cache Line=(Block Address)mod (Number of Cache Lines)\text{Cache Line} = (\text{Block Address}) \mod (\text{Number of Cache Lines})
Diagram:
Main Memory Blocks Cache Lines
------------------- ------------
Block 0 ----------------> Line 0
Block 1 ----------------> Line 1
Block 2 ----------------> Line 2
... ...
Block N ----------------> Line (N mod Cache Size)
Advantage:
- Simple and fast hardware implementation.
Disadvantage:
- Conflict misses: two blocks mapping to the same cache line causes frequent evictions.
Part 2: Virtual Memory and Paging
Virtual Memory Concept
Virtual memory is a memory management technique where the execution of processes is not constrained by the physical memory limits.
Key Features:
- Separation of Logical and Physical Memory: Applications use logical addresses; OS maps them to physical addresses.
- On-demand memory: Only necessary parts of a program are loaded.
- Swap space: Uses disk to simulate extra memory.
Advantages:
- Run large applications on limited physical memory.
- Improved multi-tasking.
- Isolates programs for better security and stability.
- Efficient memory utilization.
Paging Mechanism
Paging divides both logical and physical memory into fixed-size units:
- Pages (logical memory)
- Frames (physical memory)
Steps:
- Logical address → divided into page number and offset.
- OS maintains a page table that maps page numbers to frame numbers.
- On access:
- If the page is in RAM → access directly.
- If not → page fault → load page from disk → update page table.
Example:
- Logical Address = 14-bit → 16 KB logical memory
- Page Size = 1 KB (2^10)
- Total Pages = 16 KB / 1 KB = 16 pages
Each logical address:
- Top 4 bits → page number
- Bottom 10 bits → offset
Advantages:
- No fragmentation (fixed size)
- Enables virtual memory
- Supports efficient memory allocation
Additional Task: Page Fault Calculation
Page Reference String:
7, 3, 1, 1, 5, 6, 3, 3, 3, 4, 6
Let’s compute page faults using:
FIFO (First-In, First-Out) Algorithm
Assume 3 frames (typical for small examples):
Simulation:
| Step | Page | Frames | Page Fault |
|---|---|---|---|
| 1 | 7 | [7] | Yes |
| 2 | 3 | [7, 3] | Yes |
| 3 | 1 | [7, 3, 1] | Yes |
| 4 | 1 | [7, 3, 1] | No |
| 5 | 5 | [3, 1, 5] | Yes (7 out) |
| 6 | 6 | [1, 5, 6] | Yes (3 out) |
| 7 | 3 | [5, 6, 3] | Yes (1 out) |
| 8 | 3 | [5, 6, 3] | No |
| 9 | 3 | [5, 6, 3] | No |
| 10 | 4 | [6, 3, 4] | Yes (5 out) |
| 11 | 6 | [3, 4, 6] | No |
Total Page Faults (FIFO): 7
LRU (Least Recently Used) Algorithm
3 frames; replace the least recently used page.
| Step | Page | Frames | Page Fault |
|---|---|---|---|
| 1 | 7 | [7] | Yes |
| 2 | 3 | [7, 3] | Yes |
| 3 | 1 | [7, 3, 1] | Yes |
| 4 | 1 | [7, 3, 1] | No |
| 5 | 5 | [3, 1, 5] | Yes (7 out) |
| 6 | 6 | [1, 5, 6] | Yes (3 out) |
| 7 | 3 | [5, 6, 3] | Yes (1 out) |
| 8 | 3 | [5, 6, 3] | No |
| 9 | 3 | [5, 6, 3] | No |
| 10 | 4 | [6, 3, 4] | Yes (5 out) |
| 11 | 6 | [3, 4, 6] | No |
Total Page Faults (LRU): 7
Conclusion (Summary of Key Points)
| Concept | Summary |
|---|---|
| RAM/ROM Address Map | RAM: 0x000–0x3FF, ROM: 0x400–0x7FF |
| Hit Ratio | Hit / Total Accesses; higher = better performance |
| Direct Mapping | Maps memory blocks to specific cache lines; simple but can conflict |
| Virtual Memory | Uses disk as extended RAM; supports large apps |
| Paging | Divides memory into fixed pages/frames; managed by OS |
| Page Faults (FIFO/LRU) | Both yield 7 page faults in this exa |