Digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with three-state buffer.How many decoders are required for each bit?What will be the size of each decoder?In total, how many three-state buffers are used?
The Correct Answer and Explanation is:
To determine the number of decoders and three-state buffers required in a common bus system for 16 registers of 32 bits each, we need to understand how such a system typically operates.
1. How Many Decoders Are Required?
In a common bus system using three-state buffers, two decoders are typically used:
- One decoder for selecting the source register (for reading onto the bus).
- One decoder for selecting the destination register (for loading data from the bus).
Each decoder selects one of 16 registers, so we need:
- A 4-to-16 line decoder for source selection
- A 4-to-16 line decoder for destination selection
✅ Number of decoders per bit = 2 (shared across all bits, not per bit)
✅ Size of each decoder = 4-to-16 line decoder
2. How Many Three-State Buffers Are Required in Total?
Each bit in every register must connect to the bus via a three-state buffer, but only one register can place its value on the bus at a time.
Each register has 32 bits. To output its data to the bus, each bit needs a three-state buffer.
- Each of the 16 registers contributes 32 bits.
- So:
Total three-state buffers=16×32=512\text{Total three-state buffers} = 16 \times 32 = 512
✅ Total three-state buffers = 512
Explanation (300 words)
In a digital system with a common bus architecture, multiple registers share a single set of bus lines to transmit and receive data. The three-state buffer is critical here because it allows multiple registers to be connected to the bus without interference — only one register drives the bus at any time while others are in a high-impedance (inactive) state.
Each of the 16 registers is 32 bits wide. When a register needs to output data onto the bus, each of its 32 bits must be connected through a three-state buffer. This means each register needs 32 such buffers. Since there are 16 registers, the total number of three-state buffers required is: 16 registers×32 bits/register=512 three-state buffers16 \text{ registers} \times 32 \text{ bits/register} = 512 \text{ three-state buffers}
These buffers are enabled based on which register is selected to place data on the bus, which is controlled by a decoder. To select one of the 16 registers, a 4-bit binary input is sufficient (since 24=162^4 = 16), so a 4-to-16 line decoder is used. One decoder enables output (source register) while another decoder enables input (destination register).
Each decoder works on a control line, not per bit, and is shared among all 32 bits. Thus, two 4-to-16 decoders are used, not 32 per bit.
This arrangement minimizes complexity and allows efficient communication between multiple registers using a single bus line structure.