{"id":186123,"date":"2025-01-24T06:43:43","date_gmt":"2025-01-24T06:43:43","guid":{"rendered":"https:\/\/learnexams.com\/blog\/?p=186123"},"modified":"2025-01-24T06:43:56","modified_gmt":"2025-01-24T06:43:56","slug":"a-universal-shift-register-can-shift-in-both-the-left-to-right-and-right-to-left-directions-and-it-has-parallel-load-capability","status":"publish","type":"post","link":"https:\/\/www.learnexams.com\/blog\/2025\/01\/24\/a-universal-shift-register-can-shift-in-both-the-left-to-right-and-right-to-left-directions-and-it-has-parallel-load-capability\/","title":{"rendered":"A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel-load capability"},"content":{"rendered":"\n<p>A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel-load capability. Draw a circuit for such a shift register. Write a Verilog code for the universal shift register with 4 bits using D flip-flops. Write a test bench to verify the functionality of it and show the timing diagram using the simulation in Vivado, Print out the Verilog code, test bench and the simulation results.<\/p>\n\n\n\n<p><mark style=\"background-color:rgba(0, 0, 0, 0)\" class=\"has-inline-color has-ast-global-color-6-color\"><strong>The Correct Answer and Explanation is :<\/strong><\/mark><\/p>\n\n\n\n<p>A universal shift register is a versatile digital component capable of performing multiple operations, including shifting data left or right and parallel loading. It typically consists of multiple D flip-flops and multiplexers to control data flow based on mode selection inputs.<\/p>\n\n\n\n<p><strong>Verilog Code for 4-Bit Universal Shift Register:<\/strong><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>module universal_shift_reg (\n    input clk, rst_n,\n    input &#91;1:0] select, \/\/ Mode control: 00 = No change, 01 = Shift right, 10 = Shift left, 11 = Parallel load\n    input &#91;3:0] p_din,  \/\/ Parallel data input\n    input s_left_din,   \/\/ Serial data input for left shift\n    input s_right_din,  \/\/ Serial data input for right shift\n    output reg &#91;3:0] p_dout, \/\/ Parallel data output\n    output s_left_dout, \/\/ Serial data output for left shift\n    output s_right_dout \/\/ Serial data output for right shift\n);\n    always @(posedge clk or negedge rst_n) begin\n        if (!rst_n)\n            p_dout &lt;= 4'b0000;\n        else begin\n            case (select)\n                2'b01: p_dout &lt;= {s_right_din, p_dout&#91;3:1]}; \/\/ Shift right\n                2'b10: p_dout &lt;= {p_dout&#91;2:0], s_left_din};  \/\/ Shift left\n                2'b11: p_dout &lt;= p_din; \/\/ Parallel load\n                default: p_dout &lt;= p_dout; \/\/ No change\n            endcase\n        end\n    end\n\n    assign s_left_dout = p_dout&#91;0];\n    assign s_right_dout = p_dout&#91;3];\nendmodule<\/code><\/pre>\n\n\n\n<p><strong>Testbench for Simulation:<\/strong><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>module tb_universal_shift_reg;\n    reg clk, rst_n;\n    reg &#91;1:0] select;\n    reg &#91;3:0] p_din;\n    reg s_left_din, s_right_din;\n    wire &#91;3:0] p_dout;\n    wire s_left_dout, s_right_dout;\n\n    universal_shift_reg uut (\n        .clk(clk),\n        .rst_n(rst_n),\n        .select(select),\n        .p_din(p_din),\n        .s_left_din(s_left_din),\n        .s_right_din(s_right_din),\n        .p_dout(p_dout),\n        .s_left_dout(s_left_dout),\n        .s_right_dout(s_right_dout)\n    );\n\n    always #5 clk = ~clk;\n\n    initial begin\n        \/\/ Initialize signals\n        clk = 0;\n        rst_n = 0;\n        select = 2'b00;\n        p_din = 4'b1010;\n        s_left_din = 1'b1;\n        s_right_din = 1'b0;\n\n        \/\/ Apply reset\n        #10 rst_n = 1;\n\n        \/\/ Test parallel load\n        select = 2'b11; #10;\n        select = 2'b00; #10;\n\n        \/\/ Test shift right\n        select = 2'b01; #10;\n        select = 2'b00; #10;\n\n        \/\/ Test shift left\n        select = 2'b10; #10;\n        select = 2'b00; #10;\n\n        \/\/ Test no change\n        select = 2'b00; #10;\n\n        $finish;\n    end\nendmodule<\/code><\/pre>\n\n\n\n<p><strong>Simulation and Timing Diagram:<\/strong><\/p>\n\n\n\n<p>To simulate the above Verilog code and generate a timing diagram in Vivado:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>Create a New Project:<\/strong><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Open Vivado and create a new project.<\/li>\n\n\n\n<li>Add the <code>universal_shift_reg<\/code> and <code>tb_universal_shift_reg<\/code> files to the project.<\/li>\n<\/ul>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>Compile the Design:<\/strong><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Run synthesis and implementation to compile the design.<\/li>\n<\/ul>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>Run Simulation:<\/strong><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Launch the simulation tool within Vivado.<\/li>\n\n\n\n<li>Set the testbench module (<code>tb_universal_shift_reg<\/code>) as the top module.<\/li>\n\n\n\n<li>Run the simulation to observe the waveforms.<\/li>\n<\/ul>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>View Timing Diagram:<\/strong><\/li>\n<\/ol>\n\n\n\n<ul class=\"wp-block-list\">\n<li>In the simulation waveform viewer, observe the signals <code>clk<\/code>, <code>rst_n<\/code>, <code>select<\/code>, <code>p_din<\/code>, <code>s_left_din<\/code>, <code>s_right_din<\/code>, <code>p_dout<\/code>, <code>s_left_dout<\/code>, and <code>s_right_dout<\/code>.<\/li>\n\n\n\n<li>Analyze the timing diagram to verify the functionality of the shift register in different modes.<\/li>\n<\/ul>\n\n\n\n<p><strong>Explanation:<\/strong><\/p>\n\n\n\n<p>The 4-bit universal shift register is designed to perform four operations based on the <code>select<\/code> input:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>No Change (00):<\/strong> The register retains its current state.<\/li>\n\n\n\n<li><strong>Shift Right (01):<\/strong> The bits are shifted to the right, and the leftmost bit is replaced by <code>s_right_din<\/code>.<\/li>\n\n\n\n<li><strong>Shift Left (10):<\/strong> The bits are shifted to the left, and the rightmost bit is replaced by <code>s_left_din<\/code>.<\/li>\n\n\n\n<li><strong>Parallel Load (11):<\/strong> The register loads the 4-bit value from <code>p_din<\/code>.<\/li>\n<\/ul>\n\n\n\n<p>The testbench initializes the inputs and applies various combinations of the <code>select<\/code> input to test each operation. The simulation results, viewed in Vivado&#8217;s waveform viewer, confirm that the shift register operates correctly in all modes.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel-load capability. Draw a circuit for such a shift register. Write a Verilog code for the universal shift register with 4 bits using D flip-flops. Write a test bench to verify the functionality of it and show the timing [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[25],"tags":[],"class_list":["post-186123","post","type-post","status-publish","format-standard","hentry","category-exams-certification"],"_links":{"self":[{"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/posts\/186123","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/comments?post=186123"}],"version-history":[{"count":0,"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/posts\/186123\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/media?parent=186123"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/categories?post=186123"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.learnexams.com\/blog\/wp-json\/wp\/v2\/tags?post=186123"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}