CHAPTER 1 BASIC CONCEPTS AND

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CHAPTER 1 BASIC CONCEPTS AND

COMPUTER EVOLUTION

ANSWERS TO QUESTIONS

1.1 1.2 1.3 The term ISA is sometimes used interchangeably with computer architecture. The ISA defines the attributes that have a direct impact on the logical execution of a program, as it defines each instruction and what to do with the results.Computer organization refers to the actual implementation of the ISA on a PCB. It should be noted that the same ISA (computer architecture) can be implemented in different ways. In this case, the computers have the same architecture but different organizations.The central processing unit (CPU) is the portion of a computer that fetches and executes instructions. It consists of an ALU, a control unit, and registers. A core is an individual processing unit on a processor chip whose functionality is equivalent to that of a CPU on a single-CPU system. Other specialized processing units, such as one optimized for vector and matrix operations, are also referred to as cores.

Instruction logic: Includes the tasks involved in fetching instructions

and decoding each instruction to determine the instruction operation and the memory locations of any operands.

Arithmetic and logic unit (ALU): Performs the operation specified

by an instruction.

Load/store logic: Manages the transfer of data to and from main

memory via cache.

1.4Main memory Arithmetic and logic unit (ALU) Control unit Input–output (I/O) equipment Computer Organization and Archi tecture 11e (Global Edition) By Wi lliam Stallings (Solutions Manual All Chapters, 100% Original V erified, A+ Grade) All Chapters/Supplement files download link at the end of this file. 1 / 4

1.5Instruction logic: This includes the tasks involved in fetching

instructions and decoding each instruction to determine the instruction operation and the memory locations of any operands.

Arithmetic and logic unit (ALU): Performs the operation specified by

an instruction.

Load/store logic: Manages the transfer of data to and from main

memory via cache.In addition to the components mentioned above, the core also contains an L1 cache, split between an instruction cache (I-cache) that is used for the transfer of instructions to and from main memory, and an L1 data cache, for the transfer of operands and results.

1.6In a stored program computer, programs are represented in a form suitable for storing in memory alongside the data. The computer gets its instructions byreading them from memory, and a program can be set or altered by setting the values of a portion of memory.

1.7The Internet of things is a major driver in the proliferation of embedded systems. It is a term that refers to the expanding interconnection of smart devices, ranging from appliances to tiny sensors.

1.8Cortex-M0:

This model is designed for 8- and 16-bit applications and emphasizes low cost, ultra low power, and simplicity. It is optimized for small silicon die size (starting from 12k gates) and use in the lowest-cost chips.

Cortex-M0+:

An enhanced version of the M0 that is more energy efficient.

Cortex-M3:

This model is designed for 16- and 32-bit applications and emphasizes performance and energy efficiency. It also has comprehensive debug and trace features to enable software developers to develop their applications quickly.

Cortex-M4:

This model provides all the features of the Cortex-M3, with additional instructions to support digital signal processing tasks.

1.9In a microprocessor, all of the components of the CPU are on a single chip.

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ANSWERS TO PROBLEMS

1.1a LocationInstruction/ValueComments

• <>Constant (N) [initialized to some value]
• 1Constant; Integer value = 1

-7- b.LocationInstruction/ValueComments

• <>Constant (N) [initialized to some value]
• 1Constant (loop counter increment)
• 1Variable i (loop index value; current)
• 1Variable Y = Sum of X values (Initialized to

One) 4L LOAD M(0N AC (the max limit) 4R SUB M(2)Compute Ni AC

5L JUMP + M(6,0:19) Check AC > 0 ? [i < N]

5R JUMP + M(5,20:39)i=N; done so HALT

6L LOAD M(2) i

8L STOR M(3) AC Y

8R JUMP M(4,0:19) Continue at instruction located at address

4L 1.2a.Opcode Operand

00100001000000001000

b.Opcode Operand

00000101000000010000

• 2Constant; Integer value = 2
• 0Variable Y (initialized to integer zero);

Sum(Y)

4L LOAD M(0N AC

4R ADD M(1)AC + 1 AC

5L MUL M(0)N(N+1) AC

5R DIV M(2)AC/2 AC

6L STOR M(3) AC Y; saving the Sum in variable Y

6R JUMP M(6,20:39) Done; HALT 3 / 4

-8- 1.4 1.5 1.6 1.7The discrepancy can be explained by noting that other system components aside from clock speed make a big difference in overall system speed. In particular, memory systems and advances in I/O processing contribute to the performance ratio. A system is only as fast as its slowest link. In recent years, the bottlenecks have been the performance of memory modules and bus speed.

1.3Tasks accomplished during the fetch cycle:

During the fetch cycle, the opcode of the next instruction to be executed is loaded into the IR and the address portion is loaded into the MAR. This instruction may be taken from the IBR, or it can be obtained from memory by loading a word into the MBR, and then down to the IBR, IR, and MAR.

Tasks accomplished during the execute cycle:

This cycle is performed once the opcode is in the IR. In this cycle, the control circuitry interprets the opcode and executes the instruction by sending out the appropriate control signals to cause data to be moved or an operation to be performed by the ALU.The IAS computer supports a very limited number of instructions but also addresses 40-bit words. Therefore, storing a single instruction in a 40-bit word would leave all bits except the first 8 bits as addressable space in memory. However, the IAS computer does not have enough words in memory to require 32-bit addresses.If only one instruction was stored in each word, a majority of the space in a word would be wasted. As a result, 2 instructions are stored per word, thus ensuring that a majority of the word is not wasted.An instruction is always taken from the IBR because the operations are controlled by electronic circuitry and result in the use of data paths. To simplify the electronics, there is only one register that is used to specify the address in memory for a read or write and only one register used for the source or destination.Assume that we have a simple program that does not contain any branch instructions. In this situation, storing 2 instructions per 40-bit word increases efficiency. The number of transfers from memory would be only half of the typical number needed (when 1 instruction is stored per word) to fetch the instructions.However, if we have a program that contains many branch instructions, the situation would be different. Consider a program in which every first instruction of the word is skipped and there is a direct jump to the second instruction of the subsequent word. In such a situation, for each instruction execution, the amount of data to be fetched would be double of that actually required.

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